1. Field of the Invention
The present invention relates to a semiconductor memory device such as a dynamic random access memory (DRAAM) or a static random access memory (SRAM), and particularly, to a semiconductor memory device capable of achieving a high speed operation.
2. Description of the Related Art
In a semiconductor memory device such as a DRAM or an SRAM, a signal is transmitted in a memory mat at a comparatively long distance of a word line and a bit line. Therefore, a timing margin caused by an RC delay in the word line and bit line must be significantly taken. When a line such as the word line or bit line is regarded as a transmission line, this line is released from the RC delay, and a signal delay is obtained as only a delay caused by an electromagnetic wave speed. In general, a timing margin which is equal to or greater than 10 times a conventional margin can be allocated.
Gate electrodes of a number of transistors are connected to word lines, and sources of a number of transistors are connected to bit lines. Every time the signal states of the word line and bit line are inverted, a charge is pulled out by a gate capacitance or a source dispersion capacitance of a transistor. Losing signal energy (total amount of charge) flowing through the word line and bit line results in an RC delay, and a high speed operation is inhibited. Jpn. Pat. Appln. KOKAI Publication No. 2002-124635 describes that high speed switching of a transistor is achieved by providing a circuit for forcibly pumping up and pumping down a charge required for state transition of the transistor.